The present invention relates generally to memory cells, such as D-type flip flops, and the like, and more particularly to non-volatile memory cells which have predictable failure modes. The present invention also relates to a method of data storage and retrieval which may be employed to provide for the non-volatile storage and retrieval of data.
Semiconductor memories can generally be divided into two groups--volatile and non-volatile. The first group employs dynamic or static logic elements and techniques to store data in a pattern which can be changed by the application of external signals. One problem with this first group is that memory storage is volatile, in that power must be constantly applied to the memory cell to avoid loss of data.
The second group of memories relies on special MOS devices to retain information for very long periods of time, on the order of tens of years, even with power removed. This retention is usually achieved by application of high voltages to the gates of specially constructed transistors. This operation creates a semi-permanent change in the transistor threshold voltage which results in trapping of electric charge therein. Typical of this group of transistors are Metal-Nitride-Oxide-Semiconductor (MNOS), Floating-Gate Avalanche-Injection MOS (FAMOS) and Floating-Gate Avalanche-Injection Thin-Oxide MOS (FATMOS) transistors, and the like.
To obtain a more detailed understanding of these memory cells and the devices employed therein, reference is made to U.S. Pat. Nos. 4,132,904 and 4,175,290 which discuss volatile and non-volatile memory cells in some detail.
One particular non-volatile memory cell is the D-type cell, as it is known in the art. This memory cell is a conventional memory cell and is described in detail in a publication entitled "CMOS Data Book," published by National Semiconductor Corporation, and having publication number B-F-2087 DA-RRD125M611. The particular device of interest is device number 4013 entitled "Dual Type D Flip Flop." This logic cell is somewhat similar to a conventional J-K flip-flop and is a standard logic component.
The D-type cell may typically employ gate/inverter pairs to store data signals. This design scheme is shown in the CMOS 4013 memory cell specification cited above. As mentioned above, although data signals can be stored in this cell, when power is removed, the data is lost.